Tochi’s Portfolio V1
The first iteration of my personal website, built with HTML and CSS. A hobby project to explore front-end engineering and UI/UX design.
Skills
Python
C++
C
SystemVerilog- Git
- HTML
- CSS
Software projects
TinyInfer — ML compiler & runtime
A C++ machine learning inference engine and compiler-style runtime built from scratch. TinyInfer loads model weights, executes neural-network layers, applies graph-level optimisations, and benchmarks performance against PyTorch to explore how production ML inference systems work.
MIPS pipeline simulator
A cycle-accurate five-stage pipelined CPU with hazard detection for forwarding and stalls, plus a two-bit saturating branch predictor. Validated with MIPS assembly programs. The branch predictor reduced average CPI from 1.25 to 1.11 and stalls from 403 to 203 on the showcase program.
Hardware projects
RISC-V sparse matrix-multiplication accelerator
A custom RISC-V AI accelerator supporting ML workloads, vector instructions, and ReLU extensions. FPGA DSP units compute matrix rows in parallel, while runtime INT8 quantisation reduces memory bandwidth demands. Measured speedups reached 56.8× across sparse matrix workloads and 11.92× over the ARM Cortex-M0.
Group IC design & test project
Designed circuits for a digital clock, including a main sequencer, button sequencer, and ring oscillator. Used S-Edit and L-Edit to implement the circuits and LVS checks to verify the layout. The GDSII file was sent to TSMC for fabrication, then custom test vectors were used to validate the manufactured chip.
Embedded smart lighting system
Designed the application and transport layers for an embedded device with an RF transceiver. Defined the payload’s byte structure, control functions, destination ports, and checksum to detect corrupted packets.
